Flash memory systems have been developed which provide non-volatile data storage capability and a relatively large capacity. In attempting to increase the storage capacity of these memory systems further, the size of the individual memory cells has been significantly reduced. As will be explained, this reduction in cell size has been accompanied by a decrease in the data retention of the cell because of an increased tendency to disturb the programmed state of the cell during various memory operations, including read operations.
Referring to the drawings, FIG. 1A shows an exemplary conventional flash memory cell 10 with voltages applied for carrying out a program operation. The exemplary cell 10 is formed in a P type substrate 12. An N+ source region 14 and an N+ drain region 16 are also formed in the substrate. The source and drain regions 12 and 14 are spaced apart so as to define an intermediate channel region 12a.
A floating gate 18 is disposed above the channel region 12a and spaced apart from the channel region by a thin (100 .ANG.) gate oxide. The floating gate 18 is formed from doped polysilicon and is electrically isolated from the other cell elements except for capacitive coupling. A polysilicon control gate 22 is disposed above the floating gate 18 and is separated from the floating gate 18 by an interpoly dielectric 24.
The state of cell 10 is altered by adding charge to the floating gate 18 and removing charge from the floating gate. This difference in charge causes the threshold voltage of the cell 10 to be altered so that the state of the cell 10 can be ascertained in a read operation to be described. When the cell 10 is in an erased state, there is typically a relatively small negative charge on the floating gate. When the cell 10 is in a programmed state, there is typically a relatively large negative charge on the floating gate.
Cell 10 is shown in FIG. 1A configured for a programming operation. A positive voltage (typically +6 volts) is applied to drain 16 and the source is grounded. A large positive voltage (typically +12 volts) is applied to the control gate 22. These conditions will create an electric field which will cause electrons to be accelerated from the source region 14 to the drain region 16. In addition, an electric field will be created by the large positive voltage on the control gate 22. Some of the electrons moving from the source to the drain will have sufficient energy to pass through the gate oxide 20 and collect on the floating gate. The mechanism is sometimes referred to as hot electron injection. The amount of charge transferred to the floating gate 18 is very time dependent. A typical programming operation will require that the FIG. 1A conditions be present for a relatively long duration which may be on the order of 10 microseconds. As a comparison, a typical read operation will typically take less than a hundred nanoseconds.
FIG. 1C shows exemplary conditions for reading a flash cell. The source region 14 is grounded and the drain region is connected to a small positive voltage (typically +1 to +2 volts). A positive voltage (typically +5.5 volts) is applied to the control gate 22. The electrons present on the floating gate 18 will alter the threshold voltage of the cell, that is, the control gate to source voltage which must be applied to cause the cell to conduct one microampere of current. A cell which has not been programmed will have a relatively low threshold voltage of typically +3 volts and a programmed cell will typically have a programmed threshold voltage of +5 to +6 volts.
Assuming that cell 10 has been programmed, the gate-source voltage of +5.5 volts will be near the programmed threshold voltage so that very little current may flow. The absence of cell current will indicate that the cell has been programmed thereby indicating the state of the cell. A programmed cell indicates, by common convention, a logic "0". If the cell were in an erased state, the gate-source voltage of +5.5 volts would exceed the erased threshold voltage of +3 volts. Thus, the cell will conduct a current thereby indicating that the cell is an erased cell. By common convention, an erased cell represents a logic "1".
Although not depicted in FIG. 1C, during a read operation, the cell current is converted to a voltage which is compared with a reference voltage by a sense amplifier. The output of the sense amplifier thus will be at one state indicating that the cell was erased (a logic "1") and another state indicating that the cell was programmed (a logic "0").
FIG. 1B shows the conditions for erasing a flash cell 10. A large positive voltage, typically +10 volts is applied to the source region 14 and the drain region 16 is left floating. In addition, the control gate 22 is grounded. In most flash memories, all or a large block of cells are erased at the same time. Thus, these cells all have their source regions 14 connected in common to +10 volts, their control gates 22 connected to ground and their drain regions all floating. These conditions will result in a strong electric field being produced between the source region 14 and the floating gate 18. This field will cause electrons present on the floating gate 18 to pass through the thin gate oxide 20 and to the source region. The mechanism for transferring electrons is referred to as Fowler-Nordheim tunneling. The removal of electrons will cause the cells to change from a programmed cell to an erased cell.
In erase operations, it is possible to remove too many electrons from the floating gate 18 so that a net positive charge will remain. This will tend to reduce the threshold voltage to the point that cell current will flow even when the gate-source voltage is zero. This "overerase" condition is undesirable since a cell will conduct current even when it is not being read. This current will tend to mask the current flow of the cell actually being read thereby preventing proper memory operation.
Many erase operations include sub-operations for correcting possible overerase conditions. One such sub-operation, is sometimes called a "heal" cycle. As will be explained, the heal cycle functions to both correct for overerase, and function to reduce the distribution of the erases threshold voltage of the cells so that they are more uniform after an erase operation.
In a heal cycle, the source regions 14 of all of the cells are grounded and the drain regions 16 are all left floating. In addition, the control gates are all connected to a large positive voltage, such as +12 volts. These conditions will cause an electric field to be formed between the source region 14 and the floating gate 18. The strength of the electric field will be a function of the floating gate 18 voltage, with that voltage being greater for cells that have a low threshold voltage, including those cells that have been overerased. The electric field will cause electrons to be transferred from the source region 14 to the floating gate 18, thereby increasing the erased threshold voltage of the cells. Those cells having the lowest threshold voltage will be increased the greatest amount and those having a higher threshold voltage will be affected to a much lesser extent. The heal cycle is controlled so that the erased threshold voltage of all the cells will approach some nominal value such as +3 volts.
A typical flash memory system ideally maintains a programmed state indefinitely. In practice, many memory systems are specified to retain data for periods ranging from ten years to a hundred years. A principal cause of data loss is the result of electrons being slowly removed from the floating gate 18 over time. With smaller and smaller cell geometries, the capacitances associated with the floating gates have become very small, typically on the order of a Femto Farad (10.sup.-15 Farads). Thus, removal of only a small number of electrons will result in a large change in threshold voltage.
It should also be noted that even if the state of a cell has not changed because of a change in the charge present on the floating gate, the performance of the memory may be degraded to the extent that it is no longer usable, By way of example, as the erased and programmed threshold voltages approach one another, the read error margin is reduced. In addition, the time required to perform memory operations, particularly read operations, is dependent upon the magnitude of the cell current. If, for example, the cell's erased threshold voltage is increased due to a gain of electrons on the floating gate 18, the cell may conduct sufficient current in a read operation such that the state of the cell will be correctly read. However, the increased threshold voltage will reduce the magnitude of the cell current to the point that the current will not be capable of shifting the voltage state of the array bit line sufficiently fast to carry out a read operation within memory specifications (typically on the order of a hundred nanoseconds).
There are two principal mechanisms that affect the ability of a flash memory to retain data over a long time period. One mechanism is sometimes referred to as "read disturb" and the other is sometimes referred to as "word line disturb". Read disturb occurs when a cell 10 is being read. As can be seen in FIG. 1C, a read operation creates an electric field between the source region 14 and drain region 16 due to the positive voltage (+1 to +2 volts) applied to the drain region. A very small number of electrons traveling between the drain and source regions will have sufficient energy to be drawn up to the floating gate 18 due to the positive control gate 22 voltage. Thus, the cell is very slightly programmed by way of hot electron injection in the region adjacent the drain 16 in a read operation. This is true even though the time required to perform a read operations is much less than that required to perform a conventional programming operation. The strength of the electric field between the drain and source is inversely proportional to the length of the channel 12a, with such channel length becoming smaller as cell geometries become smaller. Accordingly, this read disturb phenomena becomes more pronounced as cell sizes are reduced.
Word line disturb occurs under various conditions where a large positive voltage is applied to the control gate 22 of the cell 10, with the control gate of a cell being connected to the array word line. By way of example, in the above-described heal cycle, the source region 14 is grounded and the control gate is connected to +12 volts. These conditions result in a small number of electrons being transferred from the source region 14 to the floating gate 18 by way of Fowler-Nordheim tunneling.
Although the read and word line disturb phenomena result in only a very small transfer of electrons, it should be remembered that there may be several hundred thousand read operations for a single programming operation. Further, the capacitances associated with the floating gates of small geometry cells are so small that a change in charge due to a transfer of only a few thousand electrons will result in a floating gate potential change of one volt.
The present invention is directed to a flash memory system having improved immunity to the above-noted affects of read and word line disturb. This is accomplished without the necessity of modifying the cell geometry and without altering the basic mechanisms for performing programming, reading and erasing operations. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.